FIG. 1 is a block diagram of a memory device in the prior art.
Referring to FIG. 1, the conventional memory device comprises a command buffer 19 for receiving and buffering a command signal, a command translating unit 20 for translating the command signal that is buffered at the command buffer 19, an address buffer 10 for receiving and buffering an address, an address latching unit 11 for receiving and latching the address that is buffered at the address buffer 10, a pre-decoder 12 for pre-decoding the address that is latched by the address latching unit 11, a main decoder 13 for decoding the address that is pre-decoded by the pre-decoder 12, a memory core 14 having a number of unit cells for outputting data that is stored at one of the unit cell which is selected by the address that is decoded by the main decoder 13, an I/O sense amplifying unit 15 for sensing and amplifying the data signal that is outputted from the memory core 14, an I/O sense amplifier output controlling unit 16 for controlling output of the data that is sensed and amplified at the I/O amplifying unit 15, a multiplexer 17 for receiving the data that is outputted from the I/O sense amplifier output controlling unit 16 to output the data that is multiplexed depending on x4, x8 or x16 mode, and a data output buffer 18 for adjusting the latency of the data that is outputted from the data multiplexer 17 to output the data to external.
FIGS. 2A and 2B show circuit diagrams of a delay 29 shown in FIG. 1, in which the address that is latched by the address latching unit 11 is delayed by a predetermined time to be outputted to the data multiplexer 17. The delay 21 may be constituted with serially coupled inverters, or a RC delay of a resistor and a capacitor, as shown in FIGS. 2A and 2B.
FIG. 3 offers a partial circuit diagram of an I/O sense amplifying unit shown in FIG. 1.
Referring to FIG. 3, the I/O sense amplifier unit 15 senses and amplifies a number of data lines through which a number of data are inputted from the memory core 14, respectively, to transfer the data to the I/O sense amplifier output controlling unit 16. Describing more in detail, the I/O sense amplifier 15 includes a connecting unit 15_1 for connecting the data lines IO, /IO, through which the data are inputted from the memory core 14, to a sense amplifier 15-3 in response to a connection/disconnection signal (ISO), a pre-charging unit 15_2 for pre-charging the two IO lines IO, /IO to a pre-charge voltage, the I/O sense amplifier 15_3 for sensing and amplifying the voltage on the IO line, and a data outputting unit 15_4 for latching and transferring the data signal that is sensed and amplified by the I/O sense amplifier 15_3.
FIG. 4 provides a partial circuit diagram of an I/O sense amplifier output controlling unit shown in FIG. 1.
Referring to FIG. 4, the I/O sense amplifier output controlling unit 16 outputs the data signal A that is outputted from the I/O sense amplifier unit 15 to the data multiplexer 17 in response to an I/O sense amplifier output enable signal IOSA_output. Describing more in detail, the I/O sense amplifier output controlling unit 16 includes an inverter I3 for receiving the I/O sense amplifier output enable signal IOSA_output, an inverter I4 serially coupled to the inverter I3, 3-stage inverters I5, I6 for transferring the data signal A that is outputted from the I/O sense amplifying unit 15 depending on the output signal of the inverters I3, I4, a MOS transistor MP5 for receiving the output of the 3-stage inverter I5 at its gate and a power voltage VDD at its one end to make its output to a high level, and a MOS transistor MN11 for receiving the output of the 3-stage inverter I6 at its gate and a ground voltage VSS at its one end to make its output to a low level. Further, the I/O sense amplifier output controlling unit 16 includes a MOS transistor MP4 for receiving the signal from the inverter I3 at its gate to transfer the power voltage VDD to the gate of the MOS transistor MP5, and a MOS transistor MP4 for receiving the signal from the inverter I4 at its gate to transfer the power voltage VDD VSS to the gate of the MOS transistor MP5.
Here, the 3-stage inverters I5, I6 are enabled when the output signal of the inverter I4 is in the low level and the output signal of the inverter I3 is in the high level.
FIG. 5A to 5C represent waveform diagrams for explaining the operation of the memory device shown in FIG. 1.
It will be described for the operation of the memory device in the prior art with reference to FIG. 1 to FIG. 4 and FIG. 5A to 5C.
First, when the address is inputted to the memory device to read the data, the command is buffered at the command buffer 19 and then outputted to the command translating unit 20 where the inputted command is translated.
Also, the address is buffered at the address buffer 10 and then inputted to the address latching unit 11 where the address is latched and is outputted to the pre-decoder 12 and the delay 21.
The pre-decoder 12 pre-decodes the inputted address and then outputs the pre-decoded address to the main decoder 13 where decodes once again the pre-decoded address to output it to the memory core 14. The memory core 14 selects one of the unit cells depending on the decoded value from the main decoder 13 and outputs the data that is stored at the selected unit cell. Here, address decoding is performed in the two stages to prevent a decoder from having a large area, because the more integrated the memory device becomes, the more number of address signals are to be decoded.
Further, the I/O sense amplifying unit 15 senses and amplifies the data signal that is inputted to the I/O line depending on the I/O sense amplifier enable signal IOSA_enable from the command translating unit 20 to output it to the I/O sense amplifier output controlling unit 16.
The data that is inputted to the I/O sense amplifier output controlling unit 16 is outputted to the data multiplexer 17 in response to the output enable signal IOSA_output.
On the other hand, the address AD_L that is latched by the address latching unit 11 is delayed by the delay 21 by the predetermined time to be outputted as a delayed address AD_D to the data multiplexer 17.
The data multiplexer 17 outputs the data that is transferred from the I/O sense amplifier output controlling unit 16 to the data output buffer 18 depending on the delayed address AD_D. The data output buffer 18 adjusts the latency of the data from the data multiplexer 17 by the corresponding read command to output it to external.
FIG. 5A is a waveform diagram for explaining the operation when the power voltage VDD is in a normal status, e.g., when the operation voltage is 3.3 v, the actually inputted power voltage is 3.3 v, in the memory device shown in FIG. 1.
The address corresponding to the inputted read command Read is outputted to the address latching unit 11 as the address AD that is buffered by the address buffer 19. The address AD_L that is latched by the address latching unit 11 is outputted as the address AD_D that is delayed by the delay 21 to be outputted to the data multiplexer 17.
On the other hand, the I/O sense amplifying unit 15 is enabled by the I/O sense amplifier enable signal IOSA_enable that is outputted from the command translating unit 20 to sense and amplify the data signal on the I/O line. The sensed and amplified data is outputted to the data multiplexer 17 through the I/O sense amplifier output controlling unit 16.
At this time, the reason for making the delayed address AD_D by passing the latched address AD_L through the delay 21 is to adjust the skew between the address that is inputted into the data multiplexer 17 and the data that is inputted from the previous I/O sense amplifier output controlling unit 16.
Accordingly, the margin between the data that is transferred from the I/O sense amplifier output controlling unit 16 and the latched address is adjusted by the delay 21. As described above, the delay 21 may be constituted with the serially coupled inverters or the RC delay.
Here, tAA(Column Address Access Time) means a column address access time, i.e., the margin from input of the delayed address AD_D to input of the data into the data multiplexer 17. Also, tCCD(Column Address Dealy Time) means a column address delay time, i.e., the margin from transfer of the data from the I/O sense amplifier output controlling unit 16 to the end of input of the delayed address AD_D.
The timing shown in FIG. 5A describes the normal operation when the expected power voltage VDD is normally inputted to the operation voltage.
However, when the inputted power voltage VDD is lower or higher than the operation voltage, i.e., when the inputted power voltage VDD varies, the varying skew between the address signal that is inputted to the data multiplexer 17 and the data that is transferred from the I/O sense amplifier output controlling unit 16 could not be perfectly adjusted by only the simple delay 21 due to the circuits of each block on the data transfer path and parasitic capacitance/parasitic resistance.
Further, the skew between the address signal that is inputted to the data multiplexer 17 and the data that is transferred from the I/O sense amplifier output controlling unit 16 can vary due to the manufacturing process of the memory device, which could not be adjusted by that simple delay, either.
FIG. 5B shows a waveform diagram for explaining the operation when the power voltage VDD is lower than the operation voltage.
When the power voltage VDD is lower than the expected operation voltage, e.g., when the power voltage is 3.0 v while the operation voltage is 3.3 v, the timing at the delayed address AD_D is inputted to the data multiplexer 17 is later than the normal case because the delay time for the address during the delay 21 increases.
As shown in FIG. 5B, because the delayed address AD_D is inputted to the data multiplexer 17 lately, the margin of tAA becomes almost disappeared.
On the other hand, FIG. 5C shows a waveform diagram for explaining the operation when the power voltage VDD is higher than the operation voltage.
When the power voltage VDD is higher than the expected operation voltage, e.g., when the power voltage is 3.6 v while the operation voltage is 3.3 v, the timing at the delayed address AD_D is inputted to the data multiplexer 17 is earlier than the normal case because the delay time for the address during the delay 21 decreases.
As shown in FIG. 5C, because the delayed address AD_D is inputted early to the data multiplexer 17 compared with the normal case, the margin of tCCD becomes almost disappeared.
The above problem occurs because the characteristics of the parasitic capacitance and the parasitic resistance of the delay 21 that delays the latched address become different from those of the transfer path of the data from the memory core due to the variance of the power voltage that is inputted as the operation voltage. Also, the problem could occur because of the variance of the delay due to the process as well as the power voltage.
Accordingly, it makes it impossible to develop a memory device operating at a high speed because the variance of the power voltage or the manufacture process have effect on the variance of the skew due to difference between the data transfer path and the address transfer path.